An elementary memory cell of SRAM type is a volatile memory cell, that is to say one that loses its data in the event of a power cut, but that offers a very rapid access speed and infinite cycling.
A nonvolatile elementary memory cell, for example, a memory cell of EEPROM type, allows the data item to be preserved in the event of a power cut but cannot be cycled indefinitely.
A memory cell associating an SRAM elementary cell and one or more (for example two or four) nonvolatile cells makes it possible to combine the advantages of the two approaches, namely the speed and the infinite endurance of the SRAM memory and the nonvolatility of the nonvolatile memory—flash or EEPROM memory for example.
Under normal operating conditions, a data item is written and read to/from a memory cell of this kind in the elementary cell of SRAM type. On the other hand, notably when there is a power cut, the content of the SRAM elementary cell is transferred to the nonvolatile elementary memory cell(s) associated therewith.
Then, notably when power returns, the data contained in the nonvolatile memory cells are reloaded into the corresponding SRAM elementary memory cell.
Examples of architectures of such memory cells associating SRAM memory and nonvolatile memory are described in the documents U.S. Pat. No. 4,132,905, U.S. Pat. No. 4,467,451, U.S. Pat. No. 4,980,859, U.S. Pat. No. 7,164,608 and U.S. Pat. No. 8,018,768 and in the French patent applications filed under the numbers 1355439 (corresponding to US 2014/0369120), 1355440 (corresponding to US 2014/0369119) and 1356720 (corresponding to US 2015/0016188).
There is a risk of accidental bit flipping in the SRAM elementary cell, i.e., of the logic value of the datum stored in the SRAM memory in the flip-flop formed by the two inverters of this memory being inverted. In other words, if, at a given instant, a low logic level is present at the output of one of the inverters and a high logic level is present at the output of the other inverter, bit flipping results in the high logic level being replaced by the low logic level and vice versa, thereby leading to the stored datum being inverted.
These bit-flipping errors, also referred to by those skilled in the art as “soft errors”, may be caused by interference created by particles such as alpha particles or even cosmic rays, or even by the memory device being attacked by a laser beam.
One solution currently used to suppress these bit-flipping errors consists in using error-correcting codes and in physically separating bits belonging to a given error correction group.